By Nadine Collaert
This ebook covers the most very important equipment architectures which were commonly researched to increase the transistor scaling: FinFET. beginning with idea, the publication discusses the benefits and the combination demanding situations of this gadget structure. It addresses intimately the themes reminiscent of high-density fin patterning, gate stack layout, and source/drain engineering, that have been thought of demanding situations for the mixing of FinFETs. The e-book additionally addresses circuit-related points, together with the impression of variability on SRAM layout, ESD layout, and high-T operation. It discusses a brand new machine idea: the junctionless nanowire FET.
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Extra info for CMOS Nanoelectronics: Innovative Devices, Architectures, and Applications
Fagas G. , “Simulation of quantum current oscillations in trigate SOI MOSFETs,” IEEE Trans. Electron. Devices, 57(5), 1102–1109, 2010. 62. , Manhas S. , Anand B. , “Vertical silicon nanowire gate-all-around ﬁeld eﬀect transistor based nanoscale CMOS,” IEEE Electron. Device Lett, 32(8), 1011–1013, 2011. 63. , Faynot O. , “Experimental study on carrier transport limiting phenomena in 10 nm width nanowire CMOS transistors,” IEDM Tech. Digest, 784–787, 2010. 64. Guo-Jun Zhang, Luo Z. H. , Min Joon Huang, Tay G.
From 130 to 22 nm technology nodes, the ﬁn mask or template is transferred into the photo resist (PR) using 193 lithography or 193 immersion (193i) lithography. 1. 2. 1. 2. Patterning stack for patterning ﬁns on insulator using 193i or EUV lithography. steps, in order to reach the target critical dimension (CD) for the ﬁn; once the HM has the correct CD, its pattern is transferred into the crystalline silicon (c-Si). The carbon polymer residues are stripped in a microwave chamber followed by a diluted HF clean.
Schematic representation of the patterning stack after lithography, BARC opening, PR trim and DARC opening (350 nm ﬁn pitch or 130 nm node). 5. Schematic representation of the DARC trim, HM and c-Si patterning (130 nm node). are etched only ∼25 nm of SiOC would be removed. Hence, when the ﬁn etching is completed, a dedicated SiOC removal has to be added. This additional step would induce an undesired Buried Oxide (BOX) recess. Therefore, a CF4 /CH2 F2 process was developed for consuming SiOC during the ACL2 step.
CMOS Nanoelectronics: Innovative Devices, Architectures, and Applications by Nadine Collaert