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By A. Nicolaides

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The input and output of this amplifier are differential to maximize the ac common-mode rejection. 15. The reference inputs, VREF1 and VREF2, are tied through resistors to the positive input of A2, which allows the output offset to be adjusted anywhere in the output operating range. The gain is 1 V/V from the reference pins to the output when the reference pins are used in parallel. 5 V/V when they are used to divide the supply. The ratios of Resistors RA, RB, RC, RD, and RF are trimmed to a high level of precision to allow the common-mode rejection ratio to exceed 80 dB.

REF Figure 3-52. AD8250 and AD8251 simplified schematic. The AD8250 and AD8251 user interfaces are comprised of a parallel port that allows users to set the gain in one of three different ways (Figure 3-52). A 2-bit word sent to A1 and A2 via a bus may be latched using the CLK input. An alternative is to set the gain within 1 s by using the gain port in transparent mode. The last method is to strap A1 and A2 to a high or low voltage potential, permanently setting the gain. Figure 3-51. Small signal pulse response of the AD627 (VS = 5 V, G = +10, RL = 20 k, CL = 50 pF, 20 s/horizontal division, 20 mV/vertical division).

During this phase, the nulling amp compares its two differential inputs and corrects its own offset by driving a correction voltage into its nulling port and, ultimately, onto CN_HOLD. In this fashion, the nulling amp reduces its own offset in Phase B before it corrects for the main amp’s offset in the next phase, Phase A. PREAMP V+IN A GAIN AMP B B VDIFF +VCM CSAMPLE A + – – + B VOUT A B A CHOLD B A CHOLD A B V–IN CP_HOLD VREF RG RF Figure 3-27. Detailed schematic of the preamp during Phase B.

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Electrical and Electronic Principles II by A. Nicolaides

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