By José Rodrigo Azambuja, Fernanda Kastensmidt, Visit Amazon's Jürgen Becker Page, search results, Learn about Author Central, Jürgen Becker,
This ebook describes fault tolerance strategies in line with software program and to create hybrid thoughts. they may be able to decrease performance degradation and raise mistakes detection whilst linked to functions carried out in embedded processors. assurance starts off with an intensive dialogue of the present state of the art in fault tolerance options. The authors then talk about the easiest trade-off among software-based and hardware-based suggestions and introduce novel hybrid ideas. Proposed options elevate latest fault detection premiums as much as 100 percent, whereas holding low functionality overheads in quarter and alertness execution time.
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Extra resources for Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors
1 HPCT’s workflow instructions may change and they must be updated, including relative addresses, which must be recalculated. Such modifications are very hard to be done by hand, especially when dealing with large program codes and with lots of branch instructions. In order to automate the program code transformation, we used a tool called Hardening Post Compiling Translator (HPCT), introduced by Azambuja (2010b), and improved to implement the proposed hybrid techniques. It was implemented in Java, due to its portability to any operating system with a Java Runtime Environment (JRE), and offers easy string parsing and manipulation.
1007/978-3-319-06340-9_3, © Springer International Publishing Switzerland 2014 19 20 3 Fault Tolerance Techniques for Processors Fig. 1 COTS × RadHard processor throughput the processor’s architecture, but the system’s architecture, through communication buses or by adding extra hardware modules that do not require changes inside the components from the system. The most common non-intrusive technique is called watchdog processor (MAHMOOD 1988), where a small hardware module uses the access between processor and memory to check the processor’s transitions and then monitor its behavior.
In such cases, two options arise: leave part of the memory elements unprotected or constraint the compiler to use only a subset of the available registers. The first option is the simpler one and can result in high fault detection rates when using algorithms to choose which registers to protect (CHIELLE 2012), although part of the data path will remain unprotected. The second option can still maintain the whole data path protected, but usually compilers have to increase the code and data memory usage in order to compile the original code to a subset of registers, and therefore may increase significantly the execution time overhead.
Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors by José Rodrigo Azambuja, Fernanda Kastensmidt, Visit Amazon's Jürgen Becker Page, search results, Learn about Author Central, Jürgen Becker,