By Christian Piguet
The ability intake of microprocessors is likely one of the most vital demanding situations of high-performance chips and transportable units. In chapters drawn from Piguet's lately released Low-Power Electronics layout, this quantity addresses the layout of low-power microprocessors in deep submicron applied sciences. It offers a concentrated reference for experts inquisitive about systems-on-chips, from low-power microprocessors to DSP cores, reconfigurable processors, thoughts, ad-hoc networks, and embedded software.
Low-Power Processors and structures on Chips is equipped into 3 vast sections for handy entry. the 1st part examines the layout of electronic sign processors for embedded functions and strategies for lowering dynamic and static energy on the electric and method degrees. the second one half describes numerous points of low-power structures on chips, together with and embedded software program elements, effective info garage, networks-on-chips, and functions resembling routing thoughts in instant RF sensing and actuating units. the ultimate part discusses embedded software program concerns, together with info on compilers, retargetable compilers, and coverification tools.
Providing unique examinations contributed via top specialists, Low-Power Processors and structures on Chips provides authoritative info on how one can preserve excessive functionality whereas reducing energy intake in sleek processors and SoCs. it's a must-read for somebody designing sleek pcs or embedded platforms.
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Extra info for Low-Power Processors and Systems on Chips
7] H. Wong, D. Frank, P. Solomon, H. Wann, and J. Welser, Nanaoscale CMOS, Proc. IEEE, 87, pp. 537–570, 1999.  S. Wolf, Silicon Processing for the VLSI Era: Volume 3 — The Submicron MOSFET, Lattice Press, Sunset Beach, CA, 1995.  R. Gonzalez, B. Gordon, and M. Horowitz, Supply and threshold voltage scaling for low-power CMOS, IEEE J. Solid-State Circuits, 32, pp. 1210–1216, Aug. 1997.  D. Frank, Power constrained CMOS scaling limits, IBM J. Res. , 46, 2/3, p. 235, 2002.  S. , 1999.
In practice, this is provided by generating separate signals from the same clock divider circuits, which anticipate coincident edges constituting allowed domain crossings. Ideally, the maximum core speed is half that of the PLL voltage controlled oscillator (VCO) because a 2× divide easily provides a 50:50 duty cycle clock. , the number of instructions required) instead of the number of clocks and some indicator of whether or not the machine is busy. Modern systems use an interrupt-driven model, whereby the processor will enter a low-power state, pending being awakened via interrupt, when there is no useful work to perform.
Chang and Patrick Schaumont. fm Page 14 Friday, July 1, 2005 10:02 AM 2-14 Low-Power Processors and Systems on Chips References  B. Ackland and P. D’Arcy, A new generation of DSP architectures, Proc. 1, pp. 531–536, May 1999.  S. Agarwala et al. A 600-MHz VLIW DSP, IEEE J. Solid-State Circuits, Vol. 37, No. 11, pp. 1532–1544, Nov. 2002.  D. com.  L. Bahl, J. Cocke, F. Jelinek, and J. Raviv, “Optimal decoding of linear codes for minimizing symbol error rate,” IEEE Trans. Information Theory, Vol.
Low-Power Processors and Systems on Chips by Christian Piguet