By Yervant Zorian
MCMs this day include complicated and dense VLSI units fixed into applications that permit little actual entry to inner nodes. The complexity and value linked to their try and prognosis are significant stumbling blocks to their use. Multi-Chip Module try Strategies offers cutting-edge try options for MCMs. This quantity of unique study is designed for engineers drawn to sensible implementations of MCM try out suggestions and for designers searching for cutting edge try and design-for-testability options for his or her subsequent designs.
Multi-Chip Module try Strategies involves 8 contributions via best researchers. it's designed to supply a accomplished and well-balanced assurance of the MCM try out area.
Multi-Chip Module try out Strategies has additionally been released as a distinct factor of the Journal of digital trying out: conception and Applications (JETTA, quantity 10, Numbers 1 and 2).
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Extra info for Multi-Chip Module Test Strategies
This information can be used to compute the Wafer Test and Isolation Test yields for the given component and the given component's contribution to the overall Module Test yield (where yield is defined as the number of components passing the tests at the test level divided by the total number of chips tested at the test level). The computation can be carried out by applying the following algorithm, where for the given component, Smart Substrate MCMs = number of tests, Nfc = number of fault classes and Nt!
Kim has over 20 publications in refereed journals and conferences and one patent pending. He is on the Technical Program Committees for both the MCM Test Workshop and the North Atlantic Test Workshop. He is a member of the IEEE and ISHM. S. D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 1990. He is currently an Assistant Professor with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA. Until December 1992, he was a Research Staff Member at the General Electric Research and Development Center in Schenectady, NY.
Due to the use of a single probe head and low test frequency (700 MHz), probe movement, test time and equipment costs are expected to be low. The method combines the simplicity of capacitance testing with the resolution of latent opens testing. Based on preliminary results, the technique has an opens resolution of 2Q and shorts resolution of 20 fF for high density thin film interconnections. 5. Conclusion A survey of existing test techniques for unpopulated MCM substrates has been presented. A qualitative comparison of test methods was discussed with emphasis on test time, defect resolution capability, complexity and equipment cost.
Multi-Chip Module Test Strategies by Yervant Zorian