Offset Reduction Techniques in High-Speed Analog-To-Digital by Pedro M. Figueiredo PDF

By Pedro M. Figueiredo

ISBN-10: 1402097158

ISBN-13: 9781402097157

ISBN-10: 1402097166

ISBN-13: 9781402097164

Offset aid thoughts in High-Speed Analog-to-Digital Converters analyzes, describes the layout, and provides try result of Analog-to-Digital Converters (ADCs) utilising the 3 major high-speed architectures: flash, two-step flash and folding and interpolation. the benefits and boundaries of every one are reviewed, and the thoughts hired to enhance their functionality are mentioned.

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Pipelined folding technique. As Fig. 26 shows, each folding stage now settles independently, which relaxes the settling specifications and allows to reduce the over- Offset Reduction Techniques in High-Speed ADCs 36 all power dissipation. This technique has, however, the drawback of introducing a new source of offset voltage: the mismatches in the charge injection of the switches. 26. Illustration of the output voltages of the S/H and folding stages (NFstg = 2), when the pipelined folding technique is used.

Chapter 1: High-Speed ADC Architectures 15 zero crossings are created, which allows to substitute each group of IF pre-amplifiers by just one. In this way, there is a reduction of the input capacitance, layout area and power dissipation of the pre-amplifier stage. The power dissipated on the resistive ladder decreases because there are now less pre-amplifiers disturbing the reference voltages. The number of necessary reference voltages is also reduced by a factor of IF. In [34] the extensive utilization of interpolation allowed to eliminate the reference ladder altogether.

27. Illustration of the output voltages of the T/H and folding stages (NFstg = 2), when the equalizing technique is used. To implement this technique one may also use a nonresetting S/H – as the one presented in [43] – instead of a T/H. The important fact is that the voltage applied to the folding circuits remains unchanged during their amplification phase. The positions of the zero crossings generated by the folding and interpolation circuits are deviated due to systematic errors or to random mismatches in the components.

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Offset Reduction Techniques in High-Speed Analog-To-Digital Converters Analysis Design and Tradeoff by Pedro M. Figueiredo

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