By Inna P. Vaisband, Renatas Jakushokas, Mikhail Popovich, Andrey V. Mezhiba, Selçuk Köse, Eby G. Friedman
This publication describes equipment for dispensing strength in excessive velocity, excessive complexity built-in circuits with energy degrees exceeding many tens of watts and gear offers under a volt. It presents a extensive and cohesive therapy of strength supply and administration platforms and similar layout difficulties, together with either circuit community types and layout recommendations for on-chip decoupling capacitors, offering perception and instinct into the habit and layout of on-chip strength distribution platforms. prepared into subareas to supply a extra intuitive circulate to the reader, this fourth version provides greater than 100 pages of recent content material, together with inductance versions for interdigitated buildings, layout techniques for multi-layer energy grids, complex tools for effective energy grid layout and research, and methodologies for concurrently putting on-chip a number of strength provides and decoupling capacitors. The emphasis of this extra fabric is on dealing with the complexity of on-chip energy distribution networks.
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Additional info for On-Chip Power Delivery and Management
1 Type I Interdigitated Grids with DSDG . . . . . . . . . . 2 Type II Interdigitated Grids with DSDG . . . . . . . . . 5 Paired Grids with DSDG . . . . . . . . . . . . .. . . . . . . . . . 1 Type I Paired Grids with DSDG . . . .. . . . . . . . . . 2 Type II Paired Grids with DSDG . . . . . . . . . . . . . 6 Simulation Results . . . . . . . . . . . . . . . .. . . . . . . . .
1 Interdigitated Power Distribution Grids Without Decoupling Capacitors. . . . . . . . . . . . . . 2 Paired Power Distribution Grids Without Decoupling Capacitors. . . . . . . . . . . . . . 3 Power Distribution Grids with Decoupling Capacitors . . 4 Dependence of Power Noise on the Switching Frequency of the Current Loads . . . .. . . . . . . . . . 7 Design Implications . . . . . . . . . . . . . . . . . . . .
The on-going miniaturization of integrated circuit feature size has placed significant requirements on the on-chip power and ground distribution networks. Circuit integration densities rise with each nanometer technology generation due to smaller devices and larger dies; the current density and total current increase accordingly. Simultaneously, the higher speed switching of smaller transistors produces faster current transients within the power distribution network. Both the average current and the transient current are rising exponentially with technology scaling.
On-Chip Power Delivery and Management by Inna P. Vaisband, Renatas Jakushokas, Mikhail Popovich, Andrey V. Mezhiba, Selçuk Köse, Eby G. Friedman