By Allsoot, Choi, Park
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Extra resources for Parasitic-Aware Optimization of CMOS RF Circuits
One solution to this problem is to use two asymmetric inductors in series . Recently, a fully symmetric 3-D inductor was proposed in  and is shown in Fig. 2-9. A combination of the wind-down wind-up and the windin wind-out structures, the proposed spiral winds in and down alternately after every half turn. This structure provides positive mutual coupling and avoids the need of having two separate inductors. The port locations of this structure can also be advantageous in circuit layout.
2-18. The parasitic resistance of the device is approximated with the expression given in  and is shown below: where W, L, and are gain factor, width, length, and threshold voltage of the device, respectively. The main drawback with such a capacitor is that its behavior is non-monotonic. In order to obtain a monotonic function for the capacitance, the bulk can be disconnected from the drain and source connection and tied to the most positive voltage available, namely The typical C-V behavior of an inversion-mode MOSFET (I-mode PMOS, or IMOS) is shown in Fig.
This structure provides positive mutual coupling and avoids the need of having two separate inductors. The port locations of this structure can also be advantageous in circuit layout. Simulation shows that this structure consumes 58% less area compared to that of a planar spiral, and provides a higher However, the Q is slightly lower than that of the planar spiral because it necessarily uses thinner lower metal layers with many resistive vias between layers. Fig. 2-10 shows the performance characteristics of the structure.
Parasitic-Aware Optimization of CMOS RF Circuits by Allsoot, Choi, Park