By Jean-Pierre Colinge (auth.)
Silicon-on-Insulator expertise: fabrics to VLSI, 3rd Edition, retraces the evolution of SOI fabrics, units and circuits over a interval of approximately 20 years. two decades of development, learn and improvement in which SOI fabric fabrication suggestions were born and deserted, units were invented and forgotten, yet, most significantly, 20 years within which SOI know-how has bit by bit confirmed it could actually outperform bulk silicon in each real way. The flip of the century became out to be a milestone for the semiconductor undefined, as fine quality SOI wafers all at once turned to be had in huge amounts. From then on, it took just a couple of years to witness using SOI expertise in a wealth of purposes starting from audio amplifiers and wristwatches to 64-bit microprocessors.
This booklet offers an entire and state of the art evaluation of SOI fabrics, units and circuits. SOI fabrication and characterization strategies, SOI CMOS processing, and the physics of the SOI MOSFET obtain an in-depth analysis.
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Extra info for Silicon-on-Insulator Technology: Materials to VLSI
Thus, at high temperature the coalescence of the bubbles is diffusion-limited, while at lower temperatures « 500°C) the reaction is limited by both the extraction of the hydrogen from the hydrogenrelated cavities and hydrogen diffusion. 2. ~ S :E -4 -5 -6 -7 1 1 ~I -8 -9 -10 -11 o 1/)1 9 11 10 12 13 14 15 16 17 l/kT with T in K Figure 2-31: Arrhenius plot ofthe time to split vs. annealing temperature . The implant conditions are H+, 69 keY, 6xlO 16 em".  The Ostwald ripening mechanism by which hydrogen migrates from the smaller defects into the larger ones has been confirmed by combining infrared spectroscopy and forward recoil scattering (FRS) on wafers annealed without a stiffener.
These crystallites can be removed by an insitu HCI etch step. Once the small nuclei are removed, a new epitaxial growth step is performed, followed by an etch step, and so on, until the oxide is covered by epitaxial silicon. The epitaxial growth proceeds from the 2. A). When two growth fronts, seeded from opposite sides of the oxide, join together, a continuous siliconon-insulator film is formed, which contains a low-angle subgrain boundary where the two growth fronts meet. B). lf'] The major disadvantage of the ELO technique is the nearly 1:1 lateral-to-vertical growth ratio, which means that a 10 um-thick film must be grown to cover 20 um-wide oxide patterns (10 urn from each side).
I'I''] Platelets are flat, disk-shaped microcavities containing hydrogen. Their thickness is approximately 2 lattice parameters (l nm), their diameter is approximately 10 nm, and they are mainly oriented along (100) planes along the (100) surface of the wafer. (Figure 2-28). Figure 2-28: A: Hydrogen implant ation ad formation of defects (vacancies. vacancy clusters and platelets; B: Formation of a blister upon annealing. Rp is the projected range of the implanted ions. Typical implantation dose ranges between lx10 16 and 7x10 16 H+/cm2 .
Silicon-on-Insulator Technology: Materials to VLSI by Jean-Pierre Colinge (auth.)